For wireless communication applications, radio frequency (RF) Pulse-Width Modulation/Pulse-Position Modulation (PWM-PPM) signals are promising candidates to drive high efficiency switching mode power amplifiers (SMPAs). RF PWM-PPM signals are wide-band signals that require driving the relatively high input parasitic capacitance of the SMPA transistor. Therefore, a wide-band, high-speed, digital, III-V (such as GaAs, InP, and GaN) driver circuit is desirable to reduce amplitude and phase distortion.
For this class of SMPA, a sufficient input swing around the transistor threshold voltage is required to fully turn the switch-mode transistor from the on state to the off state, so as to achieve high drain efficiency. To obtain high output power, SMPAs typically consist of a large transistor periphery, such as a long unit gate width with multiple gate fingers, resulting in a high input parasitic capacitance.
CMOS technology is typically used to produce the digital switching pulses, which are operating at much lower and different voltage ranges in comparison to III-V technology voltages. In addition, RF PWM-PPM signals contain a large amount of harmonic content, such as up to the fifth harmonic, to realize a reasonable pulse shape. For example, if the RF PWM-PPM is operating at a 6 GHz fundamental frequency, the digital driver circuit should preferably operate at up to about 30 GHz so as to avoid distortion of the pulse train. Hence, a wide-band digital III-V driver is essentially needed.
However, III-V transistors typically operate in depletion mode (−ve threshold voltage), so the implementation of a push-pull digital inverter buffer without the benefit of the enhancement-mode transistor type (+ve threshold voltage) is difficult to realize, especially with varying duty-cycle input signals. Further, there are no complementary transistors in III-V technology, as there are in CMOS technology.
This situation leads to problems, such as in the interface between the CMOS and the III-V technologies, in that the switching signals coming from the CMOS circuits need to be shifted to different bias levels prior to input to the SMPAs.
What is needed, therefore, is a circuit design that tends to reduce issues such as those described above, at least in part.